The present invention relates generally to integrated circuit (IC) packages. More particularly, the invention relates to IC packages with embedded capacitive components.
In many types of circuits, it is desirable to provide discrete components such as capacitors and inductors in combination with integrated circuits. In some circumstances, efforts have been made to incorporate a discrete component, such as a capacitor, into the package that protects the integrated circuit. By way of example, U.S. Pat. No. 6,091,144 describes a package which has a capacitor structure formed on a die pad. Other packages with integrated capacitor structures include U.S. Pat. Nos. 5,498,901 and 5,629,559. These capacitors are typically used to reduce power supply noise delivered to the integrated circuit. Although such structures likely work well, there are continuing efforts to improve the manufacturability of the packages and to improve their electrical performance.
One relatively recently developed package is a leadless leadframe style package (LLP). A LLP is a type of surface mounted integrated circuit package that uses a metal (typically copper) leadframe substrate to form a chip scale package (CSP). As illustrated in FIGS. 1a, b, and c, in known leadless leadframe packages, a copper leadframe strip or panel 101 is patterned, typically by stamping or etching, to define a plurality of arrays 103 of device areas 105. Each device area 105 includes a die attach pad 107 and a plurality of contacts 109 disposed about associated die attach pad 107. Very fine tie bars 111 are used to support the die attach pads 107 and contacts 109 during manufacturing.
During assembly, IC dice are attached to respective die attach pads 107 and conventional wire bonding is used to electrically couple bond pads on each die to associated contacts 109 within the same device area 105. After the wire bonding, a plastic cap is molded over the top surface of each device area 105 or over the entire array 103. The capped dice are then cut from the array and tested using known sawing and testing techniques.
FIG. 2 provides a cross-section of a known LLP. Die attach pad 107 supports die 120, often attached by a non-conductive resin 160. Die 120 is electrically connected to its associated contacts 109 by bonding wires 122. A molded plastic cap 125 encapsulates die 120 and bonding wires 122 and fills the gaps between die attach pad 107 and contacts 109, holding the contacts in place. During singulation, tie bars 111 are cut. The resulting packaged chip can then be surface mounted on a printed circuit board (PCB) or other substrate using known techniques. Since LLPs are growing in popularity, it would be desirable to provide simple techniques for integrating capacitor structures into such packages. It would also be desirable if the improved techniques are also applicable to some other package designs.
To achieve the foregoing and other objects of the invention, an integrated circuit package is described that includes a capacitor structure having a pair of plates separated by a dielectric material. An integrated circuit (IC) die is carried by a top surface of the first capacitor plate. The die carried by the capacitor structure is electrically connected to a multiplicity of contacts. A protective encapsulant covers the die and a portion of the capacitor structure while leaving a surface of the second capacitor plate at least partially exposed.
In some embodiments, one of the capacitor plates (typically the lower capacitor plate) is formed from the same lead frame sheet as the contacts. In LLP implementations, the lower capacitor plate is substantially co-planar with the contacts. Depending on the implementation the capacitor structure can be electrically connected in a variety of different manners. One or both of the plates can be electrically connected to either (or both of) selected bond pads on the die or selected leads or contacts.
Other features, advantages, and objects of the present invention will become more apparent and be more readily understood from the following detailed description, which should be read in conjunction with the accompanying drawings.